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 HD74HC125/HD74HC126
Quad. Bus Buffer Gates (with 3-state outputs)
REJ03D0565-0200 (Previous ADE-205-439) Rev.2.00 Oct 11, 2005
Description
The HD74HC125, HD74HC126 require the 3-state control input C to be taken high to put the output into the high impedance condition, whereas the HD74HC125, HD74HC126 requires the control input to be low to put the output into high impedance.
Features
* * * * * * High Speed Operation: tpd = 8 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 A max Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C) Ordering Information
Part Name HD74HC125P HD74HC126P HD74HC125FPEL HD74HC125FPEL HD74HC126RPEL Package Type DILP-14 pin SOP-14 pin (JEITA) SOP-14 pin (JEDEC) Package Code (Previous Code) PRDP0014AB-B (DP-14AV) PRSP0014DF-B (FP-14DAV) Package Abbreviation P FP -- EL (2,000 pcs/reel) EL (2,500 pcs/reel) ELL (2,000 pcs/reel) Taping Abbreviation (Quantity)
PRSP0014DE-A RP (FP-14DNV) HD74HC125TELL PTSP0014JA-B TSSOP-14 pin T HD74HC126TELL (TTP-14DV) Note: Please consult the sales office for the above package availability.
Function Table
Inputs C HC125 H L L H: L: X: Z: HC126 L H H X L H A HC125 Z L H Output Y HC126 Z L H
High level Low level Irrelevant Off (high-impedance) state of a 3-state output.
Rev.2.00, Oct 11, 2005 page 1 of 8
HD74HC125/HD74HC126
Pin Arrangement
* HD74HC125
1C 1A 1Y 2C 2A 2Y GND
1 2 3 4 5 6 7 (Top view)
14 13 12 11 10 9 8
VCC 4C 4A 4Y 3C 3A 3Y
* HD74HC126
1C 1A 1Y 2C 2A 2Y GND
1 2 3 4 5 6 7 (Top view)
14 13 12 11 10 9 8
VCC 4C 4A 4Y 3C 3A 3Y
Rev.2.00, Oct 11, 2005 page 2 of 8
HD74HC125/HD74HC126
Absolute Maximum Ratings
Item Supply voltage range Input voltage Output voltage Output current DC current drain per VCC, GND DC input diode current DC output diode current Power dissipation per package Storage temperature Symbol VCC VIN VOUT IOUT ICC, IGND IIK IOK PT Tstg Rating -0.5 to +7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 35 75 20 20 500 -65 to +150 Unit V V V mA mA mA mA mW C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time Note:
*1
Symbol VCC VIN, VOUT Ta tr , tf
Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500 0 to 400
Unit V V C ns
Conditions
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Ta = 25C Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 VIL 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOL 2.0 4.5 6.0 4.5 Off-state output current Input current Quiescent supply current IOZ Iin ICC 6.0 6.0 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- -- Max -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.5 0.1 4.0 Ta = -40 to+85C Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- -- Max -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 5.0 1.0 40 V IOH = -6 mA IOH = -7.8 mA Vin = VIH or VIL IOL = 20 A V Unit V Test Conditions
Output voltage
VOH
V
Vin = VIH or VIL IOH = -20 A
IOL = 6 mA IOL = 7.8 mA A Vin = VIH or VIL, Vout = VCC or GND A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A
Rev.2.00, Oct 11, 2005 page 3 of 8
HD74HC125/HD74HC126
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25C Item Propagation delay time Output enable Time Output disable Time Output rise/fall time Input capacitance Symbol VCC (V) tPLH, tPHL 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- Min -- -- -- -- -- -- -- -- -- -- -- -- -- Typ -- 8 -- -- 9 -- -- 14 -- -- 4 -- 5 Max 100 20 17 150 30 26 150 30 26 60 12 10 10 Ta = -40 to +85C Min -- -- -- -- -- -- -- -- -- -- -- -- -- Max 125 25 21 190 38 33 190 38 33 75 15 13 10 Unit ns Test Conditions
tZH, tZL
ns
tHZ, tLZ
ns
tTLH, tTHL
ns
Cin
pF
Test Circuit
VCC VCC
See Function Table
Input
C
Output 1 k S1 CL = 50 pF
Pulse generator Z OUT = 50
A
Y
*1
OPEN See under table GND
TEST t PLH /tPHL t ZH/tHZ t ZL /tLZ Note: C L includes the probe and jig capacitance.
S1 OPEN GND VCC
Rev.2.00, Oct 11, 2005 page 4 of 8
HD74HC125/HD74HC126 Waveforms * HD74HC125
* Waveform - 1
tr 90 % 50 % 10 % t PLH 90 % 50 %
tf VCC 10 % t PHL 0V
Input A
VOH Output Y 50 % 50 % VOL
* Waveform - 2
90 % 50 %
tf
tr 90 % 50 % 10 % t ZL 10 % t LZ 50 % t ZH t HZ 90 % VCC 0V VOH
Input C
Waveform - A
10 % VOL VOH VOL
Waveform - B
50 %
Notes : 1. tr 6 ns, tf 6 ns 2. Input waveform : PRR 1 MHz, duty cycle 50% 3. Waveform- A is for an output with internal conditions such that the output is low except when disabled by the output control. 4. Waveform- B is for an output with internal conditions such that the output is high except when disabled by the output control.
Rev.2.00, Oct 11, 2005 page 5 of 8
HD74HC125/HD74HC126 Waveforms * HD74HC126
* Waveform - 1
tr 90 % 50 % 10 % t PLH 90 % 50 %
tf VCC 10 % t PHL 0V
Input A
VOH Output Y 50 % 50 % VOL
* Waveform - 2
tr 90 % 50 % 10 % t ZL 90 % 50 %
tf VCC 10 % t LZ 50 % t ZH t HZ 90 % 0V VOH
Input C
Waveform - A
10 % VOL VOH VOL
Waveform - B
50 %
Notes : 1. tr 6 ns, tf 6 ns 2. Input waveform : PRR 1 MHz, duty cycle 50% 3. Waveform- A is for an output with internal conditions such that the output is low except when disabled by the output control. 4. Waveform- B is for an output with internal conditions such that the output is high except when disabled by the output control.
Rev.2.00, Oct 11, 2005 page 6 of 8
HD74HC125/HD74HC126
Package Dimensions
JEITA Package Code P-DIP14-6.3x19.2-2.54 RENESAS Code PRDP0014AB-B Previous Code DP-14AV MASS[Typ.] 0.97g
D
14
8
1 b3
7
Z
E
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 2.39 2.54 0.56 Max
A
A1
e1 D E
L
A A1 bp
e
bp
e1
c
b3 c
e Z
( Ni/Pd/Au plating )
L
JEITA Package Code P-SOP14-3.95x8.65-1.27
RENESAS Code PRSP0014DE-A
Previous Code FP-14DNV
MASS[Typ.] 0.13g
*1
D 8
F
14
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
*2
Index mark
HE
E
c
Reference Symbol
Dimension in Millimeters Min Nom 8.65 3.95 Max 9.05
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
7 bp x M L1
A1 A bp b1 c c1
0.10
0.14
0.25 1.75
0.34
0.40
0.46
0.15
0.20
0.25
A
HE
0 5.80 6.10 1.27
8 6.20
A1
L
e x y
0.25 0.15 0.635 0.40
1
y
Detail F
Z L L 0.60 1.08
1.27
Rev.2.00, Oct 11, 2005 page 7 of 8
HD74HC125/HD74HC126
JEITA Package Code P-SOP14-5.5x10.06-1.27 RENESAS Code PRSP0014DF-B Previous Code FP-14DAV MASS[Typ.] 0.23g
*1
D 8
F
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
14
bp
HE
E
Index mark
*2
c
Reference Symbol
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2 A1 0.00
7 bp x M L1
0.10
0.20 2.20
A bp b1 c c
1
0.34
0.40
0.46
0.15
0.20
0.25
A
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 1.42 0.50
1
Detail F
Z L L 0.70 1.15
0.90
JEITA Package Code P-TSSOP14-4.4x5-0.65
RENESAS Code PTSP0014JA-B
Previous Code TTP-14DV
MASS[Typ.] 0.05g
*1
D
F 8
14
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
*2
HE
E
c
Reference Symbol
Dimension in Millimeters Min Nom 5.00 4.40 Max 5.30
Index mark
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
7 bp x M L1
A1 A bp b1 c c
1
0.03
0.07
0.10 1.10
0.15
0.20
0.25
0.10
0.15
0.20
A
HE
0 6.20 6.40 0.65
8 6.60
A1
L
e x y
0.13 0.10 0.83 0.4
1
y
Detail F
Z L L 0.5 1.0
0.6
Rev.2.00, Oct 11, 2005 page 8 of 8
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
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